1. Field of the Invention
The present patent specification relates to a method and apparatus for differential voltage amplifying, and more particularly to a method and apparatus for differential voltage amplifying capable of responding to a wide range of input voltage and achieving a high gain.
2. Discussion of Background
Conventionally, background differential amplifying circuits are provided with two oppositely-conductive differential transistor pairs so as to normally operate when receiving input voltages that vary within a power source voltage range. For example, Japanese Laid-Open Patent Publications, No. 04-076246 (1992), No. 08-204470 (1996), and No. 09-093055 (1997) discuss the above-mentioned background differential amplifying circuits.
FIG. 1 illustrates a background differential amplifying circuit 100 discussed in by Japanese Laid-Open Patent Publication, No. 04-076246 (1992). In FIG. 1, the background differential amplifying circuit 100 includes first and second power source terminals V1 and V2, first and second input terminals In1 and In2, first and second differential pair circuits 101 and 102, a first current source 103 for supplying a current to the first differential pair circuit 101, a second current source 104 for supplying a current to the second differential pair circuit 102, first and second current mirror circuits 105 and 106 both connected to the first and second differential pair circuits 101 and 102, and a load circuit 107.
In FIG. 1, the first differential pair circuit 101 is connected to the first and second input terminals In1 and In2 and to the first and second output terminals OUT1 and OUT2, and is biased by the first current source 103. The second differential pair circuit 102 is connected to the first and second input terminals In1 and In2 and is biased by the second current source 104. The first current mirror circuit 105 is connected to the first power source terminal V1, the second output terminal OUT2, and one output terminal of the second differential pair circuit 102. The current mirror circuit 106 is connected to the first power source terminal V1, the first output terminal OUT1, and the other output terminal of the second differential pair circuit 102.
FIG. 2 illustrates a detailed circuit of the background differential amplifying circuit 100, using CMOS (complementary metal oxide semiconductor) transistors. In FIG. 2, the first power source terminal V1 is fed with a negative power source voltage VSS and the second power source terminal V2 is fed with a positive power source voltage VDD.
The background differential amplifying circuit 100 operates to achieve approximately 46 dB with the input voltages at a middle level in the range of the power source voltage in which the first and second differential pair circuits 101 and 102 can be both operable and, with other input voltages, approximately 40 dB by one of the two differential pair circuits 101 and 102.
Generally, a differential amplifying circuit having a negative feedback circuit produces a relatively large output error, which is an error against an expected value of an output voltage when the circuit generates a relatively small gain, without considering an offset voltage inherently provided to the differential amplifying circuit. Moreover, when the differential amplifying circuit uses oppositely-conductive differential pair circuits to allow the operations in an expanded input voltage range, it produces relatively large variations in the output voltages in response to changes in the input voltages.
Therefore, the background differential amplifying circuit 100 of Japanese Laid-Open Patent Publication, No. 04-076246 (1992) may use an output circuit having a maximum gain of approximately 30 dB, thereby increasing a total gain.
In this way, it is possible to increase the gain by adding an output circuit. However, the gain generally depends on the input voltage. For example, the gain with the input voltages at a middle level in the range of the power source voltage is greatly different from that with the input voltages close to the power source voltage. With the different gains, the output errors become different typically in the case where negative feedback is applied. In particular, with the input voltages close to the power source voltage, only one of the two differential pair circuits operates and the gain of the output circuit is reduced to nearly 0 dB. Therefore, the output error may be greater.
An operational amplifier using a differential amplifying circuit commonly uses a negative feedback circuit. FIG. 3 illustrates a background non-inverse amplifier using an operational amplifier including the background differential amplifying circuit 100, for example. In the circuit of FIG. 3, when various variables are defined as an input voltage X2, an input voltage X1, an output voltage Y, resisters R1 and R2, the input voltage X2 and the output voltage Y can be expressed respectively by the following equations;
X2={R1/(R1+R2)}*Y,
and
Y=K*(X1xe2x88x92X2+xcex94V),
wherein K represents an open loop gain and xcex94V represents an offset voltage, both inherent to a differential amplifying circuit. When xcex94V in the second equation is disregarded, the second equation is modified as follows;
Y=K*(X1xe2x88x92X2).
Based on the first and the third equations, the output voltage Y is expressed by the following fourth equation;
Y=X1/{R1/(R1+R2)+(1/K)}.
From the fourth equation, it is understood that the gain of the differential amplifying circuit affects the error of the output voltage relative to the input voltage and also that the output error is varied by the ratio of resisters and the amplitude of input voltage. In other words, the output error becomes relatively greater when the differential amplifying circuit has a relatively small gain or when the gain of the negative feedback circuit by resister is relatively large.
Japanese Laid-Open Patent Publication, No. 04-076246 further discusses an exemplary use of the above-described differential amplifying circuit 100 of FIGS. 1 and 2 in the form of a voltage follower in an A/D (analog-to-digital) converter. The differential amplifying circuit 100 forms a voltage follower and is placed as a front stage to an A/D converter. In the above fourth equation, the resister R1 is substantially infinity and the resister R2 is substantially 0. Therefore, the output voltage Y has the error of the input voltage X1 multiplied by K/(K+1). This indicates that the output error changes with a change of the input voltage X1, as in the case in which the non-inverse amplifying circuit is formed.
Japanese Laid-Open Patent Publication, No. 04-076246, indicates that the differential amplifying circuit forming a voltage follower produces variations in a range of from approximately 40 dB to approximately 70 dB. With variations of 40 dB, an output error of 1% relative to the input voltage is produced. This means that when the A/D converter and the differential amplifying circuit have the power source voltage, the A/D converter that operates for 10 bits has an error equivalent to a value ten times of the least significant bit.
For another example, there are some cases in which input voltages are amplified in order to accurately convert the input voltages with an A/D converter when the input voltages have relatively small amplitude. For example, when the non-inverse amplifying circuit of FIG. 3, using the background amplifying circuit 100, is provided as a front stage to an A/D converter, the input voltages have output errors, as explained with reference to FIG. 3. Also, the non-inverse amplifying circuit receives an adverse effect by the gain of the negative feedback circuit by the resisters in comparison with the case of the voltage follower. Accordingly, when the gain of the negative feedback circuit is relatively large, the output errors further increase.
As described above, when the differential amplifying circuit having a relatively small gain is used as the input circuit for the A/D converter, it produces errors of the input voltage input to the A/D converter and, as a result, the A/D converter degrades its accuracy in the A/D conversion.
This patent specification describes a novel differential amplifying apparatus which has first and second input terminals for receiving input voltages and first and second output terminals for outputting output voltages. In one example, a novel differential amplifying apparatus includes first and second differential pair circuits, first and second current sources, a load circuit, first and second current mirror circuits, and a first voltage amplifying circuit. The first differential pair circuit includes a pair of transistors having corresponding control electrodes connected to the first and second input terminals. The second differential pair circuit includes a pair of transistors having corresponding control electrodes connected to the first and second input terminals, and possesses conductivity with a polarity opposite from the first differential pair circuit. The first current source is connected between the first differential pair circuit and a first power source terminal and is configured to bias the first differential pair circuit. The second current source is connected between the second differential pair circuit and a second power source terminal and is configured to bias the second differential pair circuit. The load circuit is connected between the first differential pair circuit and the second power source terminal, and is configured to load the first differential pair circuit. The first current mirror circuit is connected between a corresponding output terminal of the second differential pair circuit and the first power source terminal and has an output terminal connected to the second output terminal. The second current mirror circuit is connected between a corresponding output terminal of the second differential pair circuit and the first power source terminal and has an output terminal connected to the first output terminal. The first voltage amplifying circuit is configured to amplify voltages output from output terminals of the first differential pair circuit and to output amplified voltages to the first and second output terminals.
Each of the first and second current mirror circuits may include a pair of transistors connected in a cascade connection.
The first voltage amplifying circuit may include a pair of transistors having control electrodes to which a first predetermined constant voltage is applied, amplifying voltages output from corresponding output terminals of the first differential pair circuit, and outputting amplified voltages.
The above-mentioned differential amplifying apparatus may further include a second voltage amplifying circuit configured to amplify voltages output from the first and second current mirror circuits and to output amplified voltages to the corresponding first and second output terminals.
The second voltage amplifying circuit may include a pair of transistors having control electrodes to which a second predetermined constant voltage is applied, amplifying voltages output from corresponding of the first and second current mirror circuits, and outputting amplified voltages.
The above-mentioned differential amplifying apparatus may further include a current supply circuit connected between the output terminals of the first voltage amplifying circuit and the first power source terminal and configured to bypass currents output from the respective output terminals of the first voltage amplifying circuit to the first power source terminal so as to supply currents to the first voltage amplifying circuit.
The current supply circuit may include a pair of transistors having control electrodes to which a third predetermined constant voltage is applied and bypassing the corresponding currents output from of the first voltage amplifying circuit to the first power source terminal.
The above-mentioned differential amplifying apparatus may further include a current supply circuit having input terminals connected to corresponding of the output terminals of the first voltage amplifying circuit and output terminals connected to input terminals of corresponding of the first and second current mirror circuits and configured to supply currents to the first voltage amplifying circuit when the second differential pair circuit stops its operation by bypassing the currents output from the respective output terminals of the first voltage amplifying circuit to the first power source terminals via corresponding of the first and second current mirror circuits.
The current supply circuit may include a pair of transistors having control electrodes to which a fourth predetermined constant voltage is applied, and connected between the output terminals of the first voltage amplifying circuit and the input terminals of corresponding of the first and second current mirror circuits.
The fourth predetermined voltage may be a voltage to turn on the transistors of the current supply circuit when the second differential pair circuit stops its operation.
The above-mentioned differential amplifying apparatus may further include an output circuit for amplifying the voltages output from the first and second output terminals.
This patent specification further describes a novel differential amplifying method of amplifying voltages input from first and second input terminals and outputting from first and second output terminals. In one example, this novel differential amplifying method includes the following providing and connecting steps. The providing step provides a first differential pair circuit including a pair of transistors having corresponding control electrodes. The connecting step connects control electrodes of the pair of transistors to corresponding of the first and second input terminals. The providing step provides a second differential pair circuit including a pair of transistors having conductivity with a polarity opposite from conductivity of the pair of transistors of the first differential pair circuit. The connecting step connects control electrodes of the pair of transistors to corresponding of the first and second input terminals. The connecting step connects a first current source between the first differential pair circuit and a first power source terminal to bias the first differential pair circuit. The connecting step connects a second current source between the second differential pair circuit and a second power source terminal to bias the second differential pair circuit. The connecting step connects a load circuit between the first differential pair circuit and the second power source terminal to load the first differential pair circuit. The connecting step connects a first current mirror circuit between a corresponding output terminal of the second differential pair circuit and the first power source terminal. The connecting step connects an output terminal of the first current mirror circuit to the second output terminal. The connecting step connects a second current mirror circuit between a corresponding output terminal of the second differential pair circuit and the first power source terminal. The connecting step connects an output terminal of the second current mirror circuit to the first output terminal. The connecting step connects a first voltage amplifying circuit between output terminals of the first differential pair circuit and corresponding of the first and second output terminals. The first voltage amplifying circuit amplifies the voltages output from the output terminals of the first differential pair circuit and outputs amplified voltages to the corresponding of the first and second output terminals.
Each of the first and second current mirror circuits may include transistors connected in a cascade connection.
The first voltage amplifying circuit may include a pair of transistors having control electrodes to which a first predetermined constant voltage is applied, amplifying voltages output from corresponding output terminals of the first differential pair circuit, and outputting amplified voltages.
The above-mentioned method may further include the step of connecting a second voltage amplifying circuit between the output terminals of the first and second current mirror circuits and the corresponding first and second output terminals. The second voltage amplifies circuit amplifying voltages output from the first and second current mirror circuits and outputs amplified voltages to the corresponding first and second output terminals.
The second voltage amplifying circuit may include a pair of transistors having control electrodes to which a second predetermined constant voltage is applied, amplifying voltages output from corresponding of the first and second current mirror circuits, and outputting amplified voltages.
The above-mentioned method may further include the step of connecting a current supply circuit between the output terminals of the first voltage amplifying circuit and the first power source terminal. The current supply circuit is configured to bypass currents output from the respective output terminals of the first voltage amplifying circuit to the first power source terminal so as to supply currents to the first voltage amplifying circuit.
The current supply circuit may include a pair of transistors having control electrodes to which a third predetermined constant voltage is applied and bypassing the corresponding currents output from of the first voltage amplifying circuit to the first power source terminal.
The above-mentioned method may further includes the following steps. The providing step provides a current supply circuit. The connecting step connects input terminals of the current supply circuit to corresponding of the output terminals of the first voltage amplifying circuit. The connecting step connects output terminals of the current supply circuit to input terminals of corresponding of the first and second current mirror circuits. In this method, the current supply circuit supplies currents to the first voltage amplifying circuit when the second differential pair circuit stops its operation by bypassing the currents output from the respective output terminals of the first voltage amplifying circuit to the first power source terminals via corresponding of the first and second current mirror circuits.
The current supply circuit may include a pair of transistors having control electrodes to which a fourth predetermined constant voltage is applied, and connected between the output terminals of the first voltage amplifying circuit and the input terminals of corresponding of the first and second current mirror circuits.
The fourth predetermined voltage may be a voltage to turn on the transistors of the current supply circuit when the second differential pair circuit stops its operation.
The above-mentioned method may further include the step of providing an output circuit for amplifying the voltages output from the first and second output terminals.